Lexical Conventions In Verilog

• Verilog’s lexical conventions define the basic building blocks of the language, including tokens like keywords, identifiers, numbers, and comments.

• Verilog is case-sensitive, and its syntax for whitespace, comments, and number formats closely resembles C, but with hardware-specific features.

• Understanding these conventions is essential for writing clear, error-free Verilog code and avoiding subtle bugs in digital design projects.

If you’d rather watch a concise explanation, here’s a straightforward video:

Getting Started: What Are Lexical Conventions?

When I first started with Verilog, I quickly realized that understanding its lexical conventions is like learning the alphabet before you write sentences. These conventions define how Verilog code is broken down into basic elements, called tokens. Tokens are the smallest pieces of meaning in your code-they include things like keywords, numbers, identifiers, comments, and more.

Verilog’s conventions are similar to C, so if you’ve programmed in C or Java, you’ll notice some familiar patterns. But Verilog also brings in hardware-specific twists, which are important to master if you want to avoid frustrating syntax errors.

Whitespace: The Invisible Helper

Whitespace in Verilog-spaces, tabs, and newlines-exists mainly to separate tokens. The compiler ignores whitespace, except when it’s needed to distinguish between different elements. For example, inputa is a single identifier, while input a is the keyword input followed by the identifier a.

• Whitespace is ignored outside of strings, so you can format your code for readability without affecting functionality.

• Inside strings, whitespace matters and is preserved exactly as typed.

Comments: Making Code Human-Friendly

Comments are essential for documenting your code. Verilog supports two styles:

• Single-line comments: Start with // and extend to the end of the line.

• Multi-line comments: Begin with /* and end with */. These can span several lines but cannot be nested.

Here’s a quick example:

A neat trick: you can place single-line comments inside multi-line comments, but not the other way around. This helps when you need to temporarily comment out blocks of code.

Operators: The Tools for Expression

Verilog uses three main types of operators:

Unary operators come before their operand, binary operators go between two operands, and ternary operators use two symbols to separate three operands.

Numbers: Sized, Unsized, and Special Values

Verilog offers a flexible system for specifying numbers, which is critical when modeling hardware.

Sized Numbers

A sized number specifies both the bit-width and the value, using the format:

• <size>: Number of bits (e.g., 8, 16, 32)

• <base>: Number system (b for binary, d for decimal, h for hexadecimal, o for octal)

• <number>: The value itself

Examples:

Unsized Numbers

If you omit the size, Verilog assumes a default width-usually 32 bits, but this can vary by simulator. Unsized numbers default to decimal unless a base is specified.

Examples:

• 42 is a 32-bit decimal value

• 'hFF is a 32-bit hexadecimal value

Unknown and High Impedance Values

Verilog models real hardware with two special symbols:

• x: Unknown value (e.g., uninitialized or conflicting signals)

• z: High impedance (e.g., disconnected wire or tri-state bus)

These can be used in any base and are especially useful for simulation and debugging.

Negative Numbers and Signed Values

Negative numbers are specified with a minus sign before the size:

But you can’t place a minus sign between the size and the base. Also, you can add the signed keyword for signed arithmetic, which is important for certain operations.

Strings: Handling Text in Verilog

Strings are sequences of ASCII characters enclosed in double quotes:

• Strings must be on a single line-no carriage returns allowed.

• Inside a string, whitespace and all characters are preserved.

• Strings are treated as arrays of one-byte ASCII values.

Identifiers and Keywords: Naming Things Right

Keywords

Verilog reserves certain words for language constructs. All keywords are lowercase and cannot be used as identifiers.

Examples: module, input, output, always, assign

Identifiers

Identifiers are names you give to modules, signals, variables, etc. The rules are:

• Start with a letter or underscore (_)

• Can include letters, digits, underscores, and dollar signs ($)

• Cannot start with a digit or a dollar sign

• Are case-sensitive: data, Data, and DATA are all different

Examples:

Delimiters and Special Characters

Verilog uses a set of delimiters to structure code:

Quick Reference Table: Verilog Lexical Tokens

Key Takeaways

• Lexical conventions in Verilog define the basic structure and rules for writing code, including how to use whitespace, comments, operators, numbers, strings, identifiers, and keywords.

• Verilog is case-sensitive, and its conventions for numbers, comments, and identifiers are similar to C but include hardware-specific features like x and z values.

• Mastering these conventions is essential for writing clear, correct, and maintainable Verilog code in any digital design project.

Understanding these basics will help you avoid common mistakes and write Verilog that’s both readable and reliable-an essential skill for anyone serious about VLSI and digital design.